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DATA SHEET
MOS INTEGRATED CIRCUIT
PD3799
5300 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR
The PD3799 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The PD3799 has 3 rows of 5300 pixels, and each row has a single-sided readout type of charge transfer register. And it has reset feed-through level clamp circuits, clamp pulse generation circuit and voltage amplifiers. Therefore, it is suitable for 600 dpi/A4 color image scanners, color facsimiles and so on.
FEATURES
* Valid photocell * Line spacing * Color filter * Resolution : 5300 pixels x 3 : 28 m (4 lines) Red line-Green line, Green line-Blue line : Primary colors (red, green and blue), pigment filter (with light resistance 107 lx*hour) : 24 dot/mm A4 (210 x 297 mm) size (shorter side) 600 dpi US letter (8.5" x 11") size (shorter side) * Drive clock level : CMOS output under 5 V operation * Data rate * Power supply : 4 MHz MAX. : +12 V Clamp pulse generation circuit Voltage amplifiers
* Photocell's pitch : 7 m
* On-chip circuits : Reset feed-through level clamp circuits
ORDERING INFORMATION
Part Number Package CCD linear image sensor 32-pin plastic DIP (400 mil)
PD3799CY
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S14083EJ1V0DS00 (1st edition) Date published April 1999 N CP(K) Printed in Japan
(c)
1999
PD3799
BLOCK DIAGRAM
VOD 30 GND 2 GND 11
2
25
1
24
S5299
******
Photocell (Blue)
S5300
D14
D64
D65
D66
D67
S1
S2
Transfer gate VOUT1 31 (Blue) D14 CCD analog shift register S5299 S5300
23
TG1 (Blue)
******
Photocell (Green)
D64
D65
D66
D67
S1
S2
VOUT2 (Green) 32 D14
Transfer gate CCD analog shift register S5299 S5300
22
TG2 (Green)
******
Photocell (Red)
D64
D65
D66
D67
S1
S2
Transfer gate VOUT3 (Red) 1 CCD analog shift register
10
TG3 (Red)
Clamp pulse generator
3
8
9
RB
2
1
2
DATA SHEET S14083EJ1V0DS00
PD3799
PIN CONFIGURATION (Top View) CCD linear image sensor 32-pin plastic DIP (400 mil)
* PD3799CY
Output signal 3 (Red)
VOUT3
1
32
VOUT2
Output signal 2 (Green)
Ground
GND
2 1 1 1
31
VOUT1
Output signal 1 (Blue)
Reset gate clock
RB
3
30
VOD
Output drain voltage
No connection
NC
4
29
NC
No connection
No connection
NC
5
28
NC
No connection
Internal connection
IC
6
27
IC
Internal connection
Internal connection
IC
7
26
IC
Internal connection
Shift register clock 2
2
8 Green Blue Red
25
2
Shift register clock 2
Shift register clock 1
1
9
24
1
Shift register clock 1
Transfer gate clock 3 (for Red) Ground
TG3
10
23
TG1
Transfer gate clock 1 (for Blue) Transfer gate clock 2 (for Green) Internal connection
GND
11
22
TG2
Internal connection
IC
12
21
IC
Internal connection
IC
13
20
IC
Internal connection
No connection
NC
14
19
NC
No connection
5300
5300
5300
No connection
NC
15
18
NC
No connection
No connection
NC
16
17
NC
No connection
Caution Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected.
DATA SHEET S14083EJ1V0DS00
3
PD3799
PHOTOCELL STRUCTURE DIAGRAM PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing)
7 m
4 m 3 m
Blue photocell array 4 lines (28 m)
7 m
7 m
Channel stopper
Green photocell array 4 lines (28 m)
7 m
Aluminum shield
Red photocell array
4
DATA SHEET S14083EJ1V0DS00
PD3799
ABSOLUTE MAXIMUM RATINGS (TA = +25 C)
Parameter Output drain voltage Shift register clock voltage Reset gate clock voltage Transfer gate clock voltage Operating ambient temperature Storage temperature VOD V1, V2 VRB VTG1 to VTG3 TA Tstg Symbol Ratings -0.3 to +15 -0.3 to +8 -0.3 to +8 -0.3 to +8 -25 to +60 -40 to +70 Unit V V V V C C
Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (TA = +25 C)
Parameter Output drain voltage Shift register clock high level Shift register clock low level Reset gate clock high level Reset gate clock low level Transfer gate clock high level Transfer gate clock low level Data rate VOD V1H, V2H V1L, V2L VRBH VRBL VTG1H to VTG3H VTG1L to VTG3L fRB Symbol MIN. 11.4 4.5 -0.3 4.5 -0.3 4.5 -0.3 - TYP. 12.0 5.0 0 5.0 0 V1HNote 0 1.0 MAX. 12.6 5.5 +0.5 5.5 +0.5 V1HNote +0.5 4.0 Unit V V V V V V V MHz
Note
When Transfer gate clock high level (VTG1H to VTG3H) is higher than Shift register clock high level (V1H), Image lag can increase.
DATA SHEET S14083EJ1V0DS00
5
PD3799
ELECTRICAL CHARACTERISTICS
TA = +25 C, VOD = 12 V, data rate (fRB) = 1 MHz, storage time = 5.5 ms, input signal clock = 5 Vp-p light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1mm) + HA-50 (heat absorbing filter, t = 3 mm)
Parameter Saturation voltage Saturation exposure Red Green Blue Photo response non-uniformity Average dark signal Dark signal non-uniformity Power consumption Output impedance Response Red Green Blue Image lag Offset level
Note1 Note2
Symbol Vsat SER SEG SEB PRNU ADS DSNU PW ZO RR RG RB IL VOS td TTE
Test Conditions
MIN. 2.0
TYP. 2.5 0.223 0.245 0.409
MAX. -
Unit V lx*s lx*s lx*s
VOUT = 1.0 V Light shielding Light shielding
6 0.2 1.5 360 0.5 7.8 7.1 4.2 11.2 10.2 6.1 1.5 4.0 5.5 50 92 98
20 2.0 3.0 540 1 14.6 13.3 8.0 7.0 7.0
% mV mV mW k V/lx*s V/lx*s V/lx*s % V ns %
VOUT = 1.0 V
Output fall delay time
VOUT = 1.0 V VOUT = 1.0 V, data rate = 4 MHz
Total transfer efficiency
Response peak
Red Green Blue
630 540 460 DR1 DR2 Vsat /DSNU Vsat / Light shielding Light shielding -1000 - 1666 2500 -300 1.0 +500 -
nm nm nm times times mV mV
Dynamic range
Reset feed-through noise Random noise
Note1
RFTN
Notes 1. Refer to TIMING CHART 2. 2. When the fall time of 1 (t1) is the TYP. value (refer to TIMING CHART 2).
6
DATA SHEET S14083EJ1V0DS00
PD3799
INPUT PIN CAPACITANCE (TA = +25 C, VOD = 12 V)
Parameter Shift register clock pin capacitance 1 Symbol C1 Pin name Pin No. 9 24 Shift register clock pin capacitance 2 C2 MIN. TYP. 400 400 400 400 15 100 100 100 MAX. Unit pF pF pF pF pF pF pF pF
1
2
8 25
Reset gate clock pin capacitance Transfer gate clock pin capacitance
CRB CTG
RB TG1 TG2 TG3
3 23 22 10
Remark Pins 9 and 24 (1), 8 and 25 (2) are each connected inside of the device.
DATA SHEET S14083EJ1V0DS00
7
VOUT1 to VOUT3
Optical black (49 pixels)
Valid photocell (5300 pixels)
Invalid photocell (2 pixels)
Note Input the RB pulse continuously during this period, too.
5363 5364 5365 5366 5367 5368 5369
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
61 62 63 64 65 66
8
DATA SHEET S14083EJ1V0DS00
TIMING CHART 1 (for each color)
TG1 to TG3 1 2 RB
Note Note
Invalid photocell (3 pixels)
PD3799
TIMING CHART 2 (for each color)
t1 t2
1
90 % 10 %
2
t5 t6
90 % 10 % t3 t4
RB
90 % 10 %
DATA SHEET S14083EJ1V0DS00
+
td RFTN
VOUT 10 %
_
RFTN VOS
PD3799
9
PD3799
TG1 to TG3, 1, 2 TIMING CHART
t7 90 % t9 t8
TG1 to TG3
10 % t10 90 % t11
1
2
Symbol t1, t2 t3 t4 t5, t6 t7, t8 t9 t10, t11
MIN. 0 20 110 0 0 3000 900
TYP. 25 50 250 25 50 10000 1000
MAX. - - - - - - -
Unit ns ns ns ns ns ns ns
1, 2 cross points
2
2.0 V or more
0.5 V or more
1
Remark Adjust cross points of 1 and 2 with input resistance of each pin.
10
DATA SHEET S14083EJ1V0DS00
PD3799
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage: Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure: SE Product of intensity of illumination (IX) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity: PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula.
PRNU (%) = x x 100 x x : maximum of xj - x
5300 j=1
xj
5300
x=
xj : Output voltage of valid pixel number j
VOUT
Register Dark DC level
x x
4.
Average dark signal: ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula.
5300 j=1
dj
5300 dj : Dark signal of valid pixel number j
ADS (mV) =
5.
Dark signal non-uniformity: DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV) : maximum of dj - ADS j = 1 to 5300 dj : Dark signal of valid pixel number j
VOUT ADS Register Dark DC level DSNU
DATA SHEET S14083EJ1V0DS00
11
PD3799
6. Output impedance: ZO Impedance of the output pins viewed from outside. 7. Response: R Output voltage divided by exposure (Ix*s). Note that the response varies with a light source (spectral characteristic). 8. Image Lag: IL The rate between the last output voltage and the next one after read out the data of a line.
TG
Light
ON
OFF
VOUT V1 VOUT
V1 IL (%) = VOUT
x100
9.
Random noise: Random noise is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding).
100
(mV) =
(Vi - V) i=1
100
2
, V=
1
100
100 i=1
Vi
Vi: A valid pixel output signal among all of the valid pixels for each color
VOUT
V1 V2
line 1 line 2
V100
This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling).
...
line 100
...
12
DATA SHEET S14083EJ1V0DS00
PD3799
STANDARD CHARACTERISTIC CURVES (Nominal)
DARK OUTPUT TEMPERATURE CHARACTERISTIC 8 2
STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25 C)
4 Relative Output Voltage Relative Output Voltage 10 20 30 40 50 1
2
1
0.5
0.25
0.2
0.1 0
0.1
1
5 Storage Time (ms)
10
Operating Ambient Temperature TA(C)
TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter and heat absorbing filter) (TA = +25 C) 100 R
B 80
G
Response Ratio (%)
60
40
G 20
B 0 400 500 600 Wavelength (nm) 700 800
DATA SHEET S14083EJ1V0DS00
13
PD3799
APPLICATION CIRCUIT EXAMPLE
+5 V 10 + 10 F/16 V 0.1 F B3 1 2 47 3 4 NC 5 NC 6 7 4.7 8 9 10 11 12 13 14 15 16 IC IC NC IC IC 26 25 24 23 22 4.7 4.7 4.7 0.1 F 10 F/16 V VOUT3 GND + +12 V
PD3799
VOUT2 VOUT1 VOD NC 32 31 30 29 28 27 B2 B1
0.1 F 47 F/25 V
RB
RB
+5 V
+
2
4.7 4.7
2 1 TG3
GND IC IC NC NC NC
2 1 TG1 TG2
1 TG
4.7
21 IC IC NC NC NC 18 17 20 19
Caution Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected. Remark The inverters shown in the above application circuit example are the 74HC04.
14
DATA SHEET S14083EJ1V0DS00
PD3799
B1 to B3 EQUIVALENT CIRCUIT 12 V + 100 CCD VOUT 100 2SC945 47 F/25 V
2 k
DATA SHEET S14083EJ1V0DS00
15
PD3799
PACKAGE DRAWING
CCD LINEAR IMAGE SENSOR 32-PIN PLASTIC DIP (400 mil) OUTLINE DRAWINGS (Unit : mm)
1st valid pixel 4.00.3
1
9.050.3 12.60.5 54.80.5 55.20.5 4.10.5
9.250.3
10.16 (1.80)
2
(5.42) 1.020.15 0.460.06 38.1 4.550.5 2.54 4.210.5
2.580.3
3
0~1
0.250.05
0
Name Plastic cap
Dimensions 52.2x6.4x0.7 4
Refractive index 1.5
1 The 1st valid pixel 2 The surface of the chip
The center of the pin1 The top of the cap The surface of the chip
3 The bottom of the package
4 Thickness of plastic cap over CCD chip 32C-1CCD-PKG1-1
16
DATA SHEET S14083EJ1V0DS00
PD3799
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For more details, refer to our document "Semiconductor Device Mounting Technology Manual"(C10535E). Type of Through-hole Device
PD3799CY : CCD linear image sensor 32-pin plastic DIP (400 mil)
Process Partial heating method Conditions Pin temperature: 300 C or below, Heat time: 3 seconds or less (per pin)
Caution During assembly care should be taken to prevent solder or flux from contacting the plastic cap. The optical characteristics could be degraded by such contact.
DATA SHEET S14083EJ1V0DS00
17
PD3799
NOTES ON CLEANING THE PLASTIC CAP
1 CLEANING THE PLASTIC CAP
Care should be taken when cleaning the surface to prevent scratches. The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is recommended that a clean surface or cloth be used.
2 RECOMMENDED SOLVENTS
The following are the recommended solvents for cleaning the CCD plastic cap. Use of solvents other than these could result in optical or physical degradation in the plastic cap. Please consult your sales office when considering an alternative solvent.
Solvents Ethyl Alcohol Methyl Alcohol Isopropyl Alcohol N-methyl Pyrrolidone
Symbol EtOH MeOH IPA NMP
18
DATA SHEET S14083EJ1V0DS00
PD3799
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
DATA SHEET S14083EJ1V0DS00
19
PD3799
[MEMO]
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98.8

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